In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs incorporate various vertical transistor structures. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
More particularly, referring to the exemplary prior art nonplanar FET structure shown in FIG. 1, a FinFET 100 generally includes two or more parallel silicon fin structures (or simply “fins”) 104 and 106. These structures are typically formed using a silicon-on-insulator (SOI) substrate (not shown), with fins 104 and 106 extending between a common drain electrode and a common source electrode (not shown). A conductive gate structure 102 “wraps around” three sides of both fins 104 and 106, and is separated from the fins by a standard gate oxide layer 103. While FIG. 1 illustrates only one gate structure 102 wrapped around fins 104 and 106, two, three or more parallel gate structures can be wrapped around the fins. Fins 104 and 106 may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the near surface of the fins adjacent to gate oxide 103. The width of the gate, indicated by double-headed arrow 108, determines the effective channel length of the device.
While the use of stress-inducing materials is a well-known technique to increase the mobility of carriers within gate channels of planar MOSFETs, the use of such materials in FinFET structures is more difficult because of the small dimensions of FinFET features. As such devices decrease in dimension but increase in function, the pitch of parallel gates typically decreases because of the number of gates needed in a given area. In turn, as the gate pitch decreases, so too do the areas of the fins between the parallel gates. The small areas between the gates limit the width of source/drain-forming spacers that can be formed about the gates. If the width of the source/drain-forming spacers is too small, subsequently-formed source/drain regions in these areas can encroach into the channels underlying the gates, causing device failure. In addition, such small source/drain regions make it difficult to uniformly deposit an adequate amount of stress-inducing material between the gates to induce stress in the channels.
Accordingly, it is desirable to provide methods for fabricating scalable FinFET structures with stressed source/drain regions. In addition, it is desirable to provide methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers. It is also desirable to provide FinFET structures with stress-inducing source/drain-forming spacers. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.